首页>ISPLSI2064V-100LJ84I>规格书详情
ISPLSI2064V-100LJ84I中文资料PDF规格书
相关芯片规格书
更多- ISPLSI2032VL-180LB49
- ISPLSI2032VL-110LT44
- ISPLSI2032VL-135LT44
- ISPLSI2032VL-135LT48
- ISPLSI2032VL-110LJ44
- ISPLSI2032VL-180LJ44
- ISPLSI2032VL-180LT48
- ISPLSI2032VL-135LJ44
- ISPLSI2032VL-110LB49
- ISPLSI2032VL-135LT44I
- ISPLSI2032VL
- ISPLSI2032VL-180LT44
- ISPLSI2064V-100LJ44
- ISPLSI2064V-100LJ44I
- ISPLSI2064V-100LJ84
- ISPLSI2032VE300LT48I
- ISPLSI2032VE300LTN48I
- ISPLSI2032VE300LT48
ISPLSI2064V-100LJ84I规格书详情
Description
The ispLSI 2064V is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064V features in-system programmability through the Boundary Scan Test Access Port (TAP). The ispLSI 2064V offers non-volatile reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems.
Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• 3.3V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
— The 64 I/O Pin Version is Fuse Map Compatible with 5V ispLSI 2064
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 100MHz Maximum Operating Frequency
— tpd = 7.5ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100 Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
产品属性
- 型号:
ISPLSI2064V-100LJ84I
- 制造商:
LATTICE
- 制造商全称:
Lattice Semiconductor
- 功能描述:
3.3V High Density Programmable Logic
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
LAT |
05+ |
原厂原装 |
4302 |
只做全新原装真实现货供应 |
询价 | ||
Latice |
23+ |
QFP |
2 |
询价 | |||
Lattice |
23+ |
TQFP |
1005 |
全新原装现货 |
询价 | ||
LAT |
12 |
原装正品长期供货,如假包赔包换 徐小姐13714450367 |
询价 | ||||
LATTICE/莱迪斯 |
2022 |
QFP |
80000 |
原装现货,OEM渠道,欢迎咨询 |
询价 | ||
ISPLSI2064V-100LT44 |
25 |
25 |
询价 | ||||
LAT |
23+ |
589610 |
新到现货 原厂一手货源 价格秒杀代理! |
询价 | |||
LAT |
最新 |
11756 |
原装正品 现货供应 价格优 |
询价 | |||
LATTICE |
23+ |
NA |
25060 |
只做进口原装,终端工厂免费送样 |
询价 | ||
LATTICE |
21+ |
QFP |
50000 |
全新原装正品现货,支持订货 |
询价 |