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ISPLSI2064V-100LJ44中文资料PDF规格书

ISPLSI2064V-100LJ44
厂商型号

ISPLSI2064V-100LJ44

功能描述

3.3V High Density Programmable Logic

文件大小

179.68 Kbytes

页面数量

14

生产厂商 Lattice Semiconductor Corporation
企业简称

Lattice莱迪思半导体

中文名称

莱迪思半导体官网

原厂标识
数据手册

下载地址一下载地址二

更新时间

2024-5-21 17:25:00

ISPLSI2064V-100LJ44规格书详情

Description

The ispLSI 2064V is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064V features in-system programmability through the Boundary Scan Test Access Port (TAP). The ispLSI 2064V offers non-volatile reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems.

Features

• HIGH DENSITY PROGRAMMABLE LOGIC

— 2000 PLD Gates

— 64 and 32 I/O Pin Versions, Four Dedicated Inputs

— 64 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• 3.3V LOW VOLTAGE 2064 ARCHITECTURE

— Interfaces with Standard 5V TTL Devices

— The 64 I/O Pin Version is Fuse Map Compatible with 5V ispLSI 2064

• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY

— fmax = 100MHz Maximum Operating Frequency

— tpd = 7.5ns Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100 Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

产品属性

  • 型号:

    ISPLSI2064V-100LJ44

  • 制造商:

    LATTICE

  • 制造商全称:

    Lattice Semiconductor

  • 功能描述:

    3.3V High Density Programmable Logic

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LATTICE
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假一罚十原包原标签常备现货!
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只做全新原装真实现货供应
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