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ISPLSI2064V-60LT100中文资料PDF规格书
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ISPLSI2064V-60LT100规格书详情
Description
The ispLSI 2064V is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064V features in-system programmability through the Boundary Scan Test Access Port (TAP). The ispLSI 2064V offers non-volatile reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems.
Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• 3.3V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
— The 64 I/O Pin Version is Fuse Map Compatible with 5V ispLSI 2064
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 100MHz Maximum Operating Frequency
— tpd = 7.5ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100 Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
产品属性
- 型号:
ISPLSI2064V-60LT100
- 制造商:
Lattice Semiconductor Corporation
- 功能描述:
COMPLEX-EEPLD, 64-CELL, 20NS PROP DELAY, 100 Pin, Plastic, QFP
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
LATTICE |
22+23+ |
TQFP |
40443 |
绝对原装正品全新进口深圳现货 |
询价 | ||
LATTICE/莱迪斯 |
TQFP-100 |
265209 |
假一罚十原包原标签常备现货! |
询价 | |||
LATTICE |
15+ |
NA |
1863 |
只有原装!只做原装!一片起卖! |
询价 | ||
lattice |
23+ |
QFP |
8000 |
全新原装现货,欢迎来电咨询 |
询价 | ||
LATTICE |
99+ |
TQFP |
13 |
询价 | |||
Lattice |
16+ |
TQFP |
970 |
进口原装现货/价格优势! |
询价 | ||
LATTICE/莱迪斯 |
2021+ |
QFP |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
询价 | ||
LATTICE |
23+ |
TQFP-100 |
8000 |
只做原装现货 |
询价 | ||
LATTICE |
20+ |
TQFP |
2860 |
原厂原装正品价格优惠公司现货欢迎查询 |
询价 | ||
LATT |
2000 |
QFP |
1450 |
原装现货海量库存欢迎咨询 |
询价 |