155M ATM INTEGRATED SAR CONTROLLER

DESCRIPTION The µPD98405 (NEASCOT-S20TM) is a high-performance SAR chip that performs segmentation and reassembly of ATM cells. It has a PCI bus interface, a SONET/SDH 155-Mbps framer, and a clock recovery circuit and supports an ABR function in hardware. The µPD98405 conforms to ATM Forum and

文件：333.7 Kbytes 页数：64 Pages

NEC

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MOS INTEGRATED CIRCUIT

FEATURES • Conforms to ATM Forum. • Host bus interface supporting PCI bus/generic bus. - PCI interface (5/3.3 V, 32/64 bits, 33 MHz): Conforms to PCI Specification 2.1 - Generic bus interface (5/3.3 V, 32 bits, 33 MHz) • AAL-5 SAR sublayer, ATM layer, and TC sublayer functions • Hardware sup

文件：587.8 Kbytes 页数：68 Pages

RENESAS

瑞萨

155M ATM INTEGRATED SAR CONTROLLER

DESCRIPTION\nThe µPD98405 (NEASCOT-S20TM) is a high-performance SAR chip that performs segmentation and reassembly of ATM cells. It has a PCI bus interface, a SONET/SDH 155-Mbps framer, and a clock recovery circuit and supports an ABR function in hardware. The µPD98405 conforms to ATM Forum and has • Conforms to ATM Forum.\n• Host bus interface supporting PCI bus/generic bus.\n- PCI interface (5/3.3 V, 32/64 bits, 33 MHz): Conforms to PCI Specification 2.1\n- Generic bus interface (5/3.3 V, 32 bits, 33 MHz)\n• AAL-5 SAR sublayer, ATM layer, and TC sublayer functions\n• Hardware support of AAL-;

Renesas

瑞萨

155M ATM INTEGRATED SAR CONTROLLER

DESCRIPTION The µPD98405 (NEASCOT-S20TM) is a high-performance SAR chip that performs segmentation and reassembly of ATM cells. It has a PCI bus interface, a SONET/SDH 155-Mbps framer, and a clock recovery circuit and supports an ABR function in hardware. The µPD98405 conforms to ATM Forum and

文件：333.7 Kbytes 页数：64 Pages

NEC

瑞萨

MOS INTEGRATED CIRCUIT

FEATURES • Conforms to ATM Forum. • Host bus interface supporting PCI bus/generic bus. - PCI interface (5/3.3 V, 32/64 bits, 33 MHz): Conforms to PCI Specification 2.1 - Generic bus interface (5/3.3 V, 32 bits, 33 MHz) • AAL-5 SAR sublayer, ATM layer, and TC sublayer functions • Hardware sup

文件：587.8 Kbytes 页数：68 Pages

RENESAS

瑞萨

MOS INTEGRATED CIRCUIT

FEATURES • Conforms to ATM Forum. • Host bus interface supporting PCI bus/generic bus. - PCI interface (5/3.3 V, 32/64 bits, 33 MHz): Conforms to PCI Specification 2.1 - Generic bus interface (5/3.3 V, 32 bits, 33 MHz) • AAL-5 SAR sublayer, ATM layer, and TC sublayer functions • Hardware sup

文件：587.8 Kbytes 页数：68 Pages

RENESAS

瑞萨