Image Filter 11 x 10 bit, 60 MHz

Description The TMC2246A is a video-speed convolutional array composed of four 11 x 10 bit registered multipliers followed by a summer and an accumulator. All eight multiplier inputs are accessible to the user and may be updated every clock cycle with integer or fractional two’s complement data.

文件：266.11 Kbytes 页数：18 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Image Filter 11 x 10 bit, 60 MHz

Description The TMC2246A is a video-speed convolutional array composed of four 11 x 10 bit registered multipliers followed by a summer and an accumulator. All eight multiplier inputs are accessible to the user and may be updated every clock cycle with integer or fractional two’s complement data.

文件：373.82 Kbytes 页数：18 Pages

CADEKA

Image Filter 11 x 10 bit, 60 MHz

Description The TMC2246A is a video-speed convolutional array composed of four 11 x 10 bit registered multipliers followed by a summer and an accumulator. All eight multiplier inputs are accessible to the user and may be updated every clock cycle with integer or fractional two’s complement data.

文件：373.82 Kbytes 页数：18 Pages

CADEKA

Image Filter 11 x 10 bit, 60 MHz

Description The TMC2246A is a video-speed convolutional array composed of four 11 x 10 bit registered multipliers followed by a summer and an accumulator. All eight multiplier inputs are accessible to the user and may be updated every clock cycle with integer or fractional two’s complement data.

文件：266.11 Kbytes 页数：18 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Image Filter 11 x 10 bit, 60 MHz

Description The TMC2246A is a video-speed convolutional array composed of four 11 x 10 bit registered multipliers followed by a summer and an accumulator. All eight multiplier inputs are accessible to the user and may be updated every clock cycle with integer or fractional two’s complement data.

文件：266.11 Kbytes 页数：18 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Image Filter 11 x 10 bit, 60 MHz

Description The TMC2246A is a video-speed convolutional array composed of four 11 x 10 bit registered multipliers followed by a summer and an accumulator. All eight multiplier inputs are accessible to the user and may be updated every clock cycle with integer or fractional two’s complement data.

文件：373.82 Kbytes 页数：18 Pages

CADEKA