TIP630-DOC中文资料TEWS数据手册PDF规格书

Application Information

The TIP630 is an IndustryPack® compatible module providing a user configurable FPGA with 200,000 system gates. 48 I/O lines of the FPGA are directly connected to the IP I/O connector. Each I/O line has a series damping resistor and is protected against ESD and overvoltage. Six pull up resistor networks mounted in sockets are provided for the I/O lines. Pull up voltage is selectable to be either +3.3V or +5V. The I/O lines are individually programmable as input, output or tri-state I/O.

All IP bus signals of the IP interface are routed to the FPGA allowing to implement 8 MHz or 32 MHz bus interfaces with or without DMA.

Several clock sources are available at the FPGA: the IP clock (8 MHz or 32 MHz), a local 32 MHz clock and two outputs of the programmable clock generator (250 KHz – 166 MHz).

The FPGA can be configured via the IP bus or optional by a PROM which can be mounted in a socket. The configuration download for the FPGA and the programming of the clock generator is implemented by a CPLD reserving the upper two 16 bit registers of the IP I/O space. After the FPGA has been configured with the user application it can be accessed via the IP bus. The CPLD

can be used for reprogramming the FPGA without turning power off. Furthermore the CPLD offers a default ID-Prom contents which can stay active after configuring the FPGA or it can be switched off and replaced by a user ID-PROM implemented in the FPGA.

User applications can be developed using the design software ISE WebPACK which can be downloaded free of charge from www.xilinx.com .

For First Time Users the Engineering Documentation TIP630-ED is recommended. The Engineering Documentation includes TIP630-DOC, schematics, data sheets / application notes of the components and well documented sample VHDL source code.

Software support (TIP630-SW-xx) is available for different operating systems.