TC55BS4258J-12中文资料东芝数据手册PDF规格书

描述 Description

The TC55BS4258J is a 1,048,576 bit synchronous static random access memory fabricated using BICMOS technology and

organized as 262,144 words by 4 bits. The TC55BS4258J has separate data inputs and outputs and a write-cycle pass-through

feature.

Designed for pipelined architectures, this device has internal input and output registers which latch on the positive edge

of an external clock (CLK). All address, data, and control signals are latched. The setup and hold times for the inputs are 2ns

and 1ns respectively. Synchronous SRAMS can lead to faster, more robust system operation by virtually eliminating the timing

skew problems associated with conventional asynchronous SRAMs. For example, write operations are internally self-timed

when initiated - eliminating the need for accurate write pulse generation and timing by the memory controller or microproces-

sor. A pass-through feature during write cycles allows the outputs to follow the inputs with a one clock cycle delay. For read

cycles, data is available one clock cycle after the address is latched. All inputs and outputs are TTL compatible.

The TC55BS4258J is available in a 36-pin, 400mil SOJ package suitable for high density assembly.

特性 Features

• Fast cycle time

- TC55BS4258J-10

- TC55BS4258J-12

Fast clock access time

- TC55BS4258J-10

- TC55BS4258J-12

10ns (max.)

12ns (max.)

5ns (max.)

6ns (max.)

Input and output registers for synchronous operation

Data pass-through for write cycles

Single power supply: 5V ± 10

Separate data inputs and outputs

Package: JEDEC standard pinout

- 36-pin, 400mil SOJ: SOJ36-P-400