SONET OC-12/OC-3 CLOCK SYNTHESIZER

DESCRIPTION Micrels SY89426 Multi-Output Phase Locked Loop (PLL) is a SONET compliant clock generator providing 622.08MHz, 155.52MHz and retimed reference clock outputs. The PLL produces low jitter OC-12/STS-12 and OC-3/STS-3 rate clocks from an input reference clock of 38.88, 51.84, or 77.76MHz.

文件：90.57 Kbytes 页数：6 Pages

Micrel

麦瑞半导体

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High-Bandwidth's SY89426 Multi-Output Phase Locked Loop (PLL) is a SONET compliant clock generator providing 622.08MHz, 155.52MHz and retimed reference clock outputs. The PLL produces low jitter OC-12/STS-12 and OC-3/STS-3 rate clocks from an input reference clock of 38.88, 51.84, or 77.76MHz. Addit ·Single chip source for 622.08MHz and 155.52MHz clocks\n·622.08MHz output is differential PECL, 155.52MHz output is single-ended PECL\n·TTL/CMOS compatible inputs and reference output\n·SONET compliant jitter performance (≤0.01UI)\n·Choice of three reference frequencies\n·Only 395mW (typ)\n·Complies;

Microchip

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SONET OC-12/OC-3 CLOCK SYNTHESIZER

DESCRIPTION Micrels SY89426 Multi-Output Phase Locked Loop (PLL) is a SONET compliant clock generator providing 622.08MHz, 155.52MHz and retimed reference clock outputs. The PLL produces low jitter OC-12/STS-12 and OC-3/STS-3 rate clocks from an input reference clock of 38.88, 51.84, or 77.76MHz.

文件：90.57 Kbytes 页数：6 Pages

Micrel

麦瑞半导体

SONET OC-12/OC-3 CLOCK SYNTHESIZER

DESCRIPTION Micrels SY89426 Multi-Output Phase Locked Loop (PLL) is a SONET compliant clock generator providing 622.08MHz, 155.52MHz and retimed reference clock outputs. The PLL produces low jitter OC-12/STS-12 and OC-3/STS-3 rate clocks from an input reference clock of 38.88, 51.84, or 77.76MHz.

文件：90.57 Kbytes 页数：6 Pages

Micrel

麦瑞半导体

SONET OC-12/OC-3 CLOCK SYNTHESIZER

DESCRIPTION Micrels SY89426 Multi-Output Phase Locked Loop (PLL) is a SONET compliant clock generator providing 622.08MHz, 155.52MHz and retimed reference clock outputs. The PLL produces low jitter OC-12/STS-12 and OC-3/STS-3 rate clocks from an input reference clock of 38.88, 51.84, or 77.76MHz.

文件：90.57 Kbytes 页数：6 Pages

Micrel

麦瑞半导体

SONET OC-12/OC-3 CLOCK SYNTHESIZER

DESCRIPTION Micrels SY89426 Multi-Output Phase Locked Loop (PLL) is a SONET compliant clock generator providing 622.08MHz, 155.52MHz and retimed reference clock outputs. The PLL produces low jitter OC-12/STS-12 and OC-3/STS-3 rate clocks from an input reference clock of 38.88, 51.84, or 77.76MHz.

文件：90.57 Kbytes 页数：6 Pages

Micrel

麦瑞半导体

SONET OC-12/OC-3 CLOCK SYNTHESIZER

文件：78.94 Kbytes 页数：7 Pages

Micrel

麦瑞半导体

SONET OC-12/OC-3 CLOCK SYNTHESIZER

文件：78.94 Kbytes 页数：7 Pages

Micrel

麦瑞半导体

SONET OC-12/OC-3 CLOCK SYNTHESIZER

文件：78.94 Kbytes 页数：7 Pages

Micrel

麦瑞半导体

SONET OC-12/OC-3 CLOCK SYNTHESIZER

文件：78.94 Kbytes 页数：7 Pages

Micrel

麦瑞半导体