SY100EL38LZC集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

DESCRIPTION

The SY10/100EL38/L are low skew ÷2, ÷4/6 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL38/L under single-ended input conditions. As a result, this pin can only source/ sink up to 0.5mA of current.

FEATURES

■ 3.3V and 5V power supply options

■ 50ps output-to-output skew

■ Synchronous enable/disable

■ Master Reset for synchronization

■ Internal 75KΩ input pull-down resistors

■ Available in 20-pin SOIC package