5V/3.3V 첨2, 첨4/6 CLOCK GENERATION CHIP

DESCRIPTION The SY10/100EL38/L are low skew ÷2, ÷4/6 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a diff

文件：73.55 Kbytes 页数：6 Pages

Micrel

麦瑞半导体

5V/3.3V 첨2, 첨4/6 CLOCK GENERATION CHIP

DESCRIPTION The SY10/100EL38/L are low skew ÷2, ÷4/6 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a diff

文件：73.55 Kbytes 页数：6 Pages

Micrel

麦瑞半导体

5V/3.3V 첨2, 첨4/6 CLOCK GENERATION CHIP

DESCRIPTION The SY10/100EL38/L are low skew ÷2, ÷4/6 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a diff

文件：73.55 Kbytes 页数：6 Pages

Micrel

麦瑞半导体

5V/3.3V 첨2, 첨4/6 CLOCK GENERATION CHIP

DESCRIPTION The SY10/100EL38/L are low skew ÷2, ÷4/6 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a diff

文件：73.55 Kbytes 页数：6 Pages

Micrel

麦瑞半导体

5V/3.3V 첨2, 첨4/6 CLOCK GENERATION CHIP

DESCRIPTION The SY10/100EL38/L are low skew ÷2, ÷4/6 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a diff

文件：73.55 Kbytes 页数：6 Pages

Micrel

麦瑞半导体

5V/3.3V 첨2, 첨4/6 CLOCK GENERATION CHIP

DESCRIPTION The SY10/100EL38/L are low skew ÷2, ÷4/6 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a diff

文件：73.55 Kbytes 页数：6 Pages

Micrel

麦瑞半导体

IC CLK GEN /2 /4/6 5/3.3V 20SOIC

Microchip

微芯科技

IC CLK GEN /2 /4/6 5/3.3V 20SOIC

Microchip

微芯科技

IC CLK GEN /2 /4/6 3.3/5V 20SOIC

Microchip

微芯科技

Package：20-SOIC（0.295"，7.50mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLK GEN /2 /4/6 5/3.3V 20SOIC

Microchip

微芯科技