SN74LVTH162245DGGR集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF中文资料

SN74LVTH162245DGGR属于集成电路（IC）的缓冲器驱动器接收器收发器。由美国德州仪器公司制造生产的SN74LVTH162245DGGR缓冲器，驱动器，接收器，收发器逻辑缓冲器、驱动器、接收器和收发器允许隔离对某个电路的逻辑信号的访问，以用于另一电路。缓冲器将其输入信号（不变或反相）传递到其输出，并可能用于清除弱信号或驱动负载。在布尔逻辑仿真器中，缓冲器主要用于增加传播延迟。逻辑接收器和收发器允许在数据总线之间进行隔离通信。

FEATURES

· Members of the Texas Instruments Widebus™

Family

· A-Port Outputs Have Equivalent 22-W Series

Resistors, So No External Resistors Are

Required

· Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V VCC)

· Support Unregulated Battery Operation Down

to 2.7 V

· Typical VOLP (Output Ground Bounce) <0.8 V

at VCC = 3.3 V, TA = 25°C

· Ioff and Power-Up 3-State Support Hot

Insertion

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Distributed VCC and GND Pins Minimize

High-Speed Switching Noise

· Flow-Through Architecture Optimizes PCB

Layout

· Latch-Up Performance Exceeds 500 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The 'LVTH162245 devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage

(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

These devices can be used as two 8-bit transceivers or one 16-bit transceiver. The devices allow data

transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the

direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses

are effectively isolated.

The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port

outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits

data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when

the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic

HIGH or LOW level applied to prevent excess ICC and ICCZ.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown

resistors with the bus-hold circuitry is not recommended.

The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 22-W series resistors

to reduce overshoot and undershoot.