SN74LVC1G374集成电路（IC）的触发器规格书PDF中文资料

SN74LVC1G374属于集成电路（IC）的触发器。由德州仪器制造生产的SN74LVC1G374触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。

1FEATURES

2• Available in the Texas Instruments NanoStar™

and NanoFree™ Packages

• Supports 5-V V CC Operation

• Inputs Accept Voltages to 5.5 V

• Provides Down Translation to VCC

• Max tpd of 4 ns at 3.3 V

• Low Power Consumption, 10-μA Max ICC

• ±24-mA Output Drive at 3.3 V

• Ioff Supports Live Insertion, Partial-Power-

Down Mode, and Back Drive Protection

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION

This single D-type latch is designed for 1.65-V to 5.5-

V VCC operation.

The SN74LVC1G374 features a 3-state output

designed specifically for driving highly capacitive or

relatively low-impedance loads. This device is

particularly suitable for implementing buffer registers,

input/output (I/O) ports, bidirectional bus drivers, and

working registers.

NanoStar™ and NanoFree™ package technology is

a major breakthrough in IC packaging concepts,

using the die as the package.

On the positive transition of the clock (CLK) input, the

Q output is set to the logic level set up at the data (D)

input.

A buffered output-enable (OE) input can be used to

place the output in either a normal logic state (high or

low logic levels) or the high-impedance state. In the

high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance

state and increased drive provide the capability to

drive bus lines without interface or pullup

components.

OE does not affect the internal operations of the flip-

flop. Old data can be retained or new data can be

entered while the outputs are in the high-impedance

state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a

pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the

driver.

This device is fully specified for partial-power-down

applications using Ioff. The Ioff circuitry disables the

outputs, preventing damaging current backflow

through the device when it is powered down.