SN74LVC166ADR中文资料德州仪器数据手册PDF规格书

1 Features

• Operating range from 1.1V to 3.6V

• Over-voltage tolerant inputs support up to 5.5V

independent of VCC

• Supports partial-power-down with back drive

protection (Ioff)

• High push-pull output drive strength:

– ±24mA at 3.3V

– ±8mA at 2.3V

– ±4mA at 1.65V

• Maximum propagation delay of 11.2ns at 3.3V

supply

• Latch-up performance exceeds 100mA

per JESD78

2 Applications

• Increase the number of inputs on a microcontroller

• Read in board revision

3 Description

The SN74LVC166A contains one 8-bit parallel-load

shift register. Data is loaded synchronously using the

shift or load (SH/LD) select and clock (CLK) inputs.

The device includes a serial (SER) input to allow

for daisy chaining and an asynchronous clear (CLR)

input.