SN74HC646数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

The ’HC646 devices consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’HC646 devices.
Output-enable (OE)\\ and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either or both registers.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE\\ is active (low). In the isolation mode (OE\\ high), A data may be stored in one register and/or B data may be stored in the other register.
To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
When an output function is disabled, the input function is still enabled and can be used to store data. Only one of the two buses, A or B, may be driven at a time.

特性 Features

• Wide Operating Voltage Range of 2 V to 6 V
• High-Current 3-State Outputs Can Drive Up To 15 LSTTL Loads
• Low Power Consumption, 80-µA Max ICC
• Typical tpd = 11 ns
• ±6-mA Output Drive at 5 V
• Low Input Current of 1 µA Max
• Independent Registers for A and B Buses
• Multiplexed Real-Time and Stored Data
• True Data Paths