SN74GTL16622A中文资料18 位 LVTTL 到 GTL/GTL+ 总线收发器数据手册TI规格书

描述 Description

The SN74GTL16622A is an 18-bit registered bus transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. This device is partitioned as two separate 9-bit transceivers with individual clock-enable controls and contains D-type flip-flops for temporary storage of data flowing in either direction. This device provides an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC™ circuitry. The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. Data flow in each direction is controlled by the output-enable (OEAB\\ and OEBA\\) and clock (CLKAB and CLKBA) inputs. The clock-enable (CEAB\\ and CEBA\\) inputs control each 9-bit transceiver independently, which makes the device more versatile. For A-to-B data flow, the device operates on the low-to-high transition of CLKAB if CEAB\\ is low. When OEAB\\ is low, the outputs are active. When OEAB\\ is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA\\, CLKBA, and CEBA\\. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

特性 Features

• Member of Texas Instruments' Widebus™ Family
• D-Type Flip-Flops With Qualified Storage Enable
• Supports Mixed-Mode (3.3 V and 5 V) Signal Operation on A-Port and Control Inputs
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)
OEC and Widebus are trademarks of Texas Instruments.

简介

SN74GTL16622A属于集成电路（IC）的转换器电平移位器。由TI制造生产的SN74GTL16622A转换器，电平移位器逻辑转换器或电平移位器 IC 可用于在数字逻辑设备之间传递信息，这些设备可在不同/不兼容的供电电压下工作，或可实现不同的信令方式。例如，可以将需要 5 V 电源的数字输出传感器连接到具有 3.3 V I/O 电源的 FPGA，或者在 CMOS 或 TTL 等单端信令方式与 PECL 或 LVDS 等差分技术之间进行转换。