LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, 2-INPUT EXCLUSIVE-NOR GATE

1FEATURES • Single-Supply Voltage Translator • Output Level Up to Supply VCC CMOS Level – 1.8 V to 3.3 V (at VCC = 3.3 V) – 2.5 V to 3.3 V (at VCC = 3.3 V) – 1.8 V to 2.5 V (at V CC = 2.5 V) – 3.3 V to 2.5 V (at V CC = 2.5 V • Schmitt-Trigger Inputs Reject Input Noise and Provide Better Ou

文件：393.06 Kbytes 页数：15 Pages

TI

德州仪器

LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, 2-INPUT EXCLUSIVE-NOR GATE

1FEATURES • Single-Supply Voltage Translator • Output Level Up to Supply VCC CMOS Level – 1.8 V to 3.3 V (at VCC = 3.3 V) – 2.5 V to 3.3 V (at VCC = 3.3 V) – 1.8 V to 2.5 V (at V CC = 2.5 V) – 3.3 V to 2.5 V (at V CC = 2.5 V • Schmitt-Trigger Inputs Reject Input Noise and Provide Better Ou

文件：393.77 Kbytes 页数：15 Pages

TI

德州仪器

LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, 2-INPUT EXCLUSIVE-NOR GATE

文件：170.42 Kbytes 页数：11 Pages

TI

德州仪器

Low-power 2-input EXCLUSIVE-NOR gate with voltage-level translator

1. General description The 74AUP1T87 provides the single 2-input EXCLUSIVE-NOR function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T87 is designed for logic-level translation applications with input switching l

文件：234.55 Kbytes 页数：13 Pages

NEXPERIA

安世

Low-power 2-input EXCLUSIVE-NOR gate with voltage-level translator

1. General description The 74AUP1T87 provides the single 2-input EXCLUSIVE-NOR function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T87 is designed for logic-level translation applications with input switching l

文件：234.55 Kbytes 页数：13 Pages

NEXPERIA

安世

Low-power 2-input EXCLUSIVE-NOR gate with voltage-level translator

1. General description The 74AUP1T87 provides the single 2-input EXCLUSIVE-NOR function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. The 74AUP1T87 is designed for logic-level translation applications with input switching l

文件：234.55 Kbytes 页数：13 Pages

NEXPERIA

安世