SN74AUCH16374DGVR集成电路（IC）的触发器规格书PDF中文资料

SN74AUCH16374DGVR属于集成电路（IC）的触发器。由德州仪器制造生产的SN74AUCH16374DGVR触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。

1FEATURES

2• Member of the Texas Instruments Widebus™

Family

• Optimized for 1.8-V Operation and Is 3.6-V I/O

Tolerant to Support Mixed-Mode Signal

Operation

• Ioff Supports Partial-Power-Down Mode

Operation

• Sub-1-V Operable

• Max tpd of 2.8 ns at 1.8 V

• Low Power Consumption, 20 μA Max ICC

• ±8-mA Output Drive at 1.8 V

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This 16-bit edge-triggered D-type flip-flop is

operational at 0.8-V to 2.7-V VCC, but is designed

specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus

drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive

transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D)

inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.