SN74ALVCH16823DGVR集成电路（IC）的触发器规格书PDF中文资料

SN74ALVCH16823DGVR属于集成电路（IC）的触发器。由德州仪器制造生产的SN74ALVCH16823DGVR触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。

FEATURES

· Member of the Texas Instruments Widebus™

Family

· EPIC™ (Enhanced-Performance Implanted

CMOS) Submicron Process

· ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

DESCRIPTION

This 18-bit bus-interface flip-flop is designed for

1.65-V to 3.6-V VCC operation.

The SN74ALVCH16823 features 3-state outputs

designed specifically for driving highly capacitive or

relatively low-impedance loads. This device is

particularly suitable for implementing wider buffer

registers, I/O ports, bidirectional bus drivers with

parity, and working registers.

The SN74ALVCH16823 can be used as two 9-bit

flip-flops or one 18-bit flip-flop. With the clock-enable

(CLKEN) input low, the D-type flip-flops enter data on

the low-to-high transitions of the clock. Taking

CLKEN high disables the clock buffer, thus latching

the outputs. Taking the clear (CLR) input low causes

the Q outputs to go low independently of the clock.

A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without need for interface or pullup components.

The output-enable (OE) input does not affect the internal operation of the flip-flops. Old data can be retained or

new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16823 is characterized for operation from –40°C to 85°C.