SN74ALVCH16821DLR集成电路（IC）的触发器规格书PDF中文资料

SN74ALVCH16821DLR属于集成电路（IC）的触发器。由德州仪器制造生产的SN74ALVCH16821DLR触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。

FEATURES

· Member of the Texas Instruments Widebus™

Family

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

DESCRIPTION/ORDERING INFORMATION

This 20-bit bus-interface flip-flop is designed for

1.65-V to 3.6-V VCC operation.

The SN74ALVCH16821 can be used as two 10-bit

flip-flops or one 20-bit flip-flop. The 20 flip-flops are

edge-triggered D-type flip-flops. On the positive

transition of the clock (CLK) input, the device

provides true data at the Q outputs.

A buffered output-enable (OE) input can be used to

place the ten outputs in either a normal logic state

(high or low logic levels) or the high-impedance state.

In the high-impedance state, the outputs neither load

nor drive the bus lines significantly. The

high-impedance state and increased drive provide the

capability to drive bus lines without need for interface

or pullup components.

OE does not affect the internal operation of the

flip-flops. Old data can be retained or new data can

be entered while the outputs are in the

high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.