SN74ALVCH16721DL.B中文资料德州仪器数据手册PDF规格书

FEATURES

· Member of the Texas Instruments Widebus™

Family

· EPIC™ (Enhanced-Performance Implanted

CMOS) Submicron Process

· ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Package Options Include Plastic 300-mil

Shrink Small-Outline (DL), Thin Shrink

Small-Outline (DGG), and Thin Very

Small-Outline (DGV) Packages

DESCRIPTION

This 20-bit flip-flop is designed specifically for 1.65-V

to 3.6-V VCC operation.

The 20 flip-flops of the SN74ALVCH16721 are

edge-triggered D-type flip-flops with qualified clock

storage. On the positive transition of the clock (CLK)

input, the device provides true data at the Q outputs if

the clock-enable (CLKEN) input is low. If CLKEN is

high, no data is stored.

A buffered output-enable (OE) input places the 20

outputs in either a normal logic state (high or low) or

the high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus lines

significantly. The high-impedance state and increased

drive provide the capability to drive bus lines without

need for interface or pullup components. OE does not

affect the internal operation of the flip-flops. Old data

can be retained or new data can be entered while the

outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16721 is characterized for operation from -40°C to 85°C.