SN74ALVCH16374DLR.B中文资料德州仪器数据手册PDF规格书

FEATURES

· Member of the Texas Instruments Widebus™

Family

· Operates From 1.65 to 3.6 V

· Max tpd of 4.2 ns at 3.3 V

· ±24-mA Output Drive at 3.3 V

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

DESCRIPTION/ORDERING INFORMATION

This 16-bit edge-triggered D-type flip-flop is designed

for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16374 is particularly suitable for

implementing buffer registers, I/O ports, bidirectional

bus drivers, and working registers. It can be used as

two 8-bit flip-flops or one 16-bit flip-flop. On the

positive transition of the clock (CLK) input, the

Q outputs of the flip-flop take on the logic levels at

the data (D) inputs. OE can be used to place the

eight outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In the

high-impedance state, the outputs neither load nor

drive the bus lines significantly. The high-impedance

state and the increased drive provide the capability to

drive bus lines without need for interface or pullup

components.

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.