SN74ALVC16334DGGR.B中文资料德州仪器数据手册PDF规格书

FEATURES

· Member of the Texas Instruments Widebus™

Family

· Operates From 1.65 V to 3.6 V

· Max tpd of 3.2 ns at 3.3 V

· ±24-mA Output Drive at 3.3 V

· Ideal for Use in PC100 Register DIMM

· Designed to Comply With JEDEC 168-Pin and

200-Pin SDRAM Buffered DIMM Specification

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This 16-bit universal bus driver is designed for 1.65-V

to 3.6-V VCC operation.

Data flow from A to Y is controlled by the

output-enable (OE) input. The device operates in the

transparent mode when the latch-enable (LE) input is

low. When LE is high, the A data is latched if the

clock (CLK) input is held at a high or low logic level. If

LE is high, the A data is stored in the latch/flip-flop on

the low-to-high transition of CLK. When OE is high,

the outputs are in the high-impedance state.

To ensure the high-impedance state during power up

or power down, OE should be tied to VCC through a

pullup resistor; the minimum value of the resistor is

determined by the current-sinking capability of the

driver.