SN74ABTH16823数据手册集成电路（IC）的触发器规格书PDF

描述 Description

These 18-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The 'ABTH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN\\) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\\ high disables the clock buffer, latching the outputs. Taking the clear (CLR\\) input low causes the Q outputs to go low independently of the clock. A buffered output-enable (OE\\) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ABTH16823 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH16823 is characterized for operation from -40°C to 85°C.

特性 Features

• Members of the Texas InstrumentsWidebusTM Family
• State-of-the-ArtEPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Typical VOLP (Output Ground Bounce) CC = 5 V, TA = 25°C
• High-Impedance State During Power Up and Power Down
• Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
• Flow-Through Architecture Optimizes PCB Layout
• High-Drive Outputs (-32-mA IOH, 64-mA IOL)
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.