SN65LVDS22PW.B中文资料德州仪器数据手册PDF规格书

FEATURES

· Meets or Exceeds the Requirements of ANSI

TIA/EIA-644-1995 Standard

· Designed for Clock Rates up to 200 MHz

(400 Mbps)

· Designed for Data Rates up to 250 Mbps

· Pin Compatible With SN65LVDS122 and

SN65LVDT122, 1.5 Gbps 2x2 Crosspoint

Switch From TI

· ESD Protection Exceeds 12 kV on Bus Pins

· Operates From a Single 3.3-V Supply

· Low-Voltage Differential Signaling With

Output Voltages of 350 mV Into:

– 100-W Load (SN65LVDS22)

– 50-W Load (SN65LVDM22)

· Propagation Delay Time; 4 ns Typ

· Power Dissipation at 400 Mbps of 150 mW

· Bus Pins Are High Impedance When Disabled

or With VCC Less Than 1.5 V

· LVTTL Levels Are 5 V Tolerant

· Open-Circuit Fail Safe Receiver

DESCRIPTION

The SN65LVDS22 and SN65LVDM22 are differential

line drivers and receivers that use low-voltage

differential signaling (LVDS) to achieve signaling

rates as high as 400 Mbps. The receiver outputs can

be switched to either or both drivers through the

multiplexer control signals S0 and S1. This allows the

flexibility to perform splitter or signal routing functions

with a single device.

The TIA/EIA-644 standard compliant electrical

interface provides a minimum differential output

voltage magnitude of 247 mV into a 100-W load and

receipt of 100 mV signals with up to 1 V of ground

potential difference between a transmitter and

receiver. The SN65LVDM22 doubles the output drive

current to achieve LVDS levels with a 50-W load.