R5F7146中文资料瑞萨数据手册PDF规格书

Overview

Features of SH7146 and SH7149

This LSI is a single-chip RISC (Reduced Instruction Set Computer) microcomputer that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration.

The CPU in this LSI has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance, and high-functioning systems, even for applications that were previously impossible with microcomputers, such as real-time control, which demands high speeds.

特性 Features

CPU

• Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture

• Instruction length: 16-bit fixed length for improved code efficiency

• Load-store architecture (basic operations are executed between registers)

• Sixteen 32-bit general registers

• Five-stage pipeline

• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits) executed in two to five cycles

• C language-oriented 62 basic instructions

Note: Some specifications on slot illegal instruction exception handling in this LSI differ from those of the conventional SH-2. For details, see section 5.8.4, Notes on Slot Illegal Instruction Exception Handling.

Operating modes

• Operating modes

 Single chip mode

 Extended ROM enabled mode (only in SH7149)

 Extended ROM disabled mode (only in SH7149)

• Operating states

 Program execution state

 Exception handling state

 Bus release state (only in SH7149)

• Power-down modes

 Sleep mode

 Software standby mode

 Deep software standby mode

 Module standby mode

User break controller

(UBC)

• Addresses, data values, type of access, and data size can all be set as break conditions

• Supports a sequential break function

• Two break channels

• In the masked ROM version, only the L bus instruction fetch address break (two channels) can be set