Low Phase Noise PLL Clock Multiplier

文件：200.39 Kbytes 页数：4 Pages

PLL

Low Phase Noise PLL Clock Multiplier

文件：200.39 Kbytes 页数：4 Pages

PLL

Low Phase Noise PLL Clock Multiplier

文件：200.39 Kbytes 页数：4 Pages

PLL

Low Phase Noise Clock Multiplier

Description The ICS601-02 is a low cost, low phase noise, high performance clock synthesizer for any application that requires low phase noise and low jitter. The ICS601 is ICS’ lowest phase noise multiplier. Using ICS’ patented analog and digital Phase Locked Loop (PLL) techniques, the chip acce

文件：80.32 Kbytes 页数：5 Pages

ICST

LOW PHASE NOISE CLOCK MULTIPLIER

Features • Packaged in 16-pin SOIC (Pb free) • Uses fundamental 10 - 27 MHz crystal or clock • Patented PLL with the lowest phase noise • Output clocks up to 170 MHz at 3.3 V • Output Enable function tri-states outptus • Low phase noise: -132 dBc/Hz at 10 kHz • Low jitter - 18 ps one sigma

文件：355.07 Kbytes 页数：9 Pages

RENESAS

瑞萨

LOW PHASE NOISE CLOCK MULTIPLIER

Description The ICS601-02 is a low cost, low phase noise, high performance clock synthesizer for any application that requires low phase noise and low jitter. The ICS601 is IDT’s lowest phase noise multiplier. Using IDT’s patented analog and digital Phase Locked Loop (PLL) techniques, the chip ac

文件：196.76 Kbytes 页数：8 Pages

IDT