PCI-to-PCI Bridge

1.1 Features The PCI2050B bridge supports the following features: • Two 32-bit, 66-MHz PCI buses • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments • Internal two-tier arbitration for up to nine secondary bus masters and supports an extern

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PCI-to-PCI Bridge

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PCI-TO-PCI BRIDGE

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PCI-to-PCI Bridge

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PCI-to-PCI Bridge

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丝印：PCI2050BIPDV；Package：LQFP；PCI-to-PCI Bridge

1.1 Features The PCI2050B bridge supports the following features: • Two 32-bit, 66-MHz PCI buses • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments • Internal two-tier arbitration for up to nine secondary bus masters and supports an extern

文件：517.51 Kbytes 页数：89 Pages

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丝印：PCI2050BIPDV；Package：LQFP；PCI-to-PCI Bridge

1.1 Features The PCI2050B bridge supports the following features: • Two 32-bit, 66-MHz PCI buses • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments • Internal two-tier arbitration for up to nine secondary bus masters and supports an extern

文件：517.51 Kbytes 页数：89 Pages

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丝印：PCI2050BIZWT；Package：NFBGA；PCI-to-PCI Bridge

1.1 Features The PCI2050B bridge supports the following features: • Two 32-bit, 66-MHz PCI buses • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments • Internal two-tier arbitration for up to nine secondary bus masters and supports an extern

文件：517.51 Kbytes 页数：89 Pages

TI

德州仪器

丝印：PCI2050BIZWT；Package：NFBGA；PCI-to-PCI Bridge

1.1 Features The PCI2050B bridge supports the following features: • Two 32-bit, 66-MHz PCI buses • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments • Internal two-tier arbitration for up to nine secondary bus masters and supports an extern

文件：517.51 Kbytes 页数：89 Pages

TI

德州仪器

丝印：PCI2050BPDV；Package：LQFP；PCI-to-PCI Bridge

1.1 Features The PCI2050B bridge supports the following features: • Two 32-bit, 66-MHz PCI buses • 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments • Internal two-tier arbitration for up to nine secondary bus masters and supports an extern

文件：517.51 Kbytes 页数：89 Pages

TI

德州仪器