Low power clock/calendar

GENERAL DESCRIPTION The PCF8593 is a CMOS clock/calendar circuit, optimized for low power consumption. Addresses and data are transferred serially via the two-line bidirectional I2C-bus. The built-in word address register is incremented automatically after each written or read data byte. The

文件：139.79 Kbytes 页数：28 Pages

PHI

飞利浦

Low power clock and calendar

General description The PCF8593 is a CMOS1 clock and calendar circuit, optimized for low power consumption. Addresses and data are transferred serially via the two-line bidirectional I2C-bus. The built-in word address register is incremented automatically after each written or read data byte. T

文件：572.41 Kbytes 页数：35 Pages

恩XP

Low power clock and calendar

General description The PCF8593 is a CMOS1 clock and calendar circuit, optimized for low power consumption. Addresses and data are transferred serially via the two-line bidirectional I2C-bus. The built-in word address register is incremented automatically after each written or read data byte. T

文件：572.41 Kbytes 页数：35 Pages

恩XP

Low power clock and calendar

General description The PCF8593 is a CMOS1 clock and calendar circuit, optimized for low power consumption. Addresses and data are transferred serially via the two-line bidirectional I2C-bus. The built-in word address register is incremented automatically after each written or read data byte. T

文件：572.41 Kbytes 页数：35 Pages

恩XP

Low power clock and calendar

The PCF8593 is a CMOS1 clock and calendar circuit, optimized for low power consumption. Addresses and data are transferred serially via the two-line bidirectional I²C-bus. The built-in word address register is incremented automatically after each written or read data byte. The built-in 32.768 kHz os I²C-bus interface operating supply voltage: 2.5 V to 6.0 V\nClock operating supply voltage 1.0 V to 6.0 V at 0 ℃ to +70 ℃\n8 bytes scratchpad RAM (when alarm not used)\nData retention voltage: 1.0 V to 6.0 V\nExternal RESET input resets I²C interface only\nOperating current (at fSCL = 0 Hz, 32 kHz t;

恩XP

恩智浦