NT5SV8M8DT-7K中文资料ETC数据手册PDF规格书

[Nanya]

Description

The NT5SV16M4DT, NT5SV8M8DT, and NT5SV4M16DT are four-bank Synchronous DRAMs organized as 4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and 1Mbit x 16 I/O x 4 Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 200MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NTC’s advanced 64Mbit single transistor CMOS DRAM process technology.

Features

• High Performance:(TABLE)

• Programmable CAS Latency: 2, 3

• Programmable Burst Length: 1, 2, 4, 8, Full page

• Programmable Wrap: Sequential or Interleave

• Multiple Burst Read with Single Write Option

• Automatic and Controlled Precharge Command

• Data Mask for Read/Write control (x4, x8)

• Dual Data Mask for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• Standard Power operation

• 4096 refresh cycles/64ms

• Random Column Address every CK (1-N Rule)

• Single 3.3V ± 0.3V Power Supply

• LVTTL compatible

• Package: 54-pin 400 mil TSOP-Type II