N74F825D中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity.

FEATURES

• High speed parallel registers with positive edge-triggered D-type flip-flops

• High performance bus interface buffering for wide data/address paths or busses carrying parity

• High impedance PNP base inputs for reduced loading (20µA in high and low states)

• IIL is 20µA vs 1000µA for AM29821 series

• Buffered control inputs to reduce AC effects

• Ideal where high speed, light loading, or increased fan-in as required with MOS microprocessor

• Positive and negative over-shoots are clamped to ground

• 3-State outputs glitch free during power-up and power-down

• Slim Dip 300 mil package

• Broadside pinout compatible with AMD AM 29821-29826 series

• Outputs sink 64mA and source 24mA

• Industrial temperature range available (–40°C to +85°C) for 74F823