MxL265D数据手册MaxLinear中文资料规格书

描述 Description

The MxL265D is a cable gateway front-end SoC that supports 16 downstream channels and 8 upstream channels (16 x 8). The MxL265D targets DOCSIS and Euro-DOCSIS cable gateway designs.

The MxL265D IC captures the full, 1GHz cable bandwidth, and is capable of providing up to 16 channels of digitized I/Q data through a SerDes interface, and has a maximum serial baud rate of 5.4Gbps. The MxL265D IC also receives digitized upstream signals from a DOCSIS back-end IC using the SerDes interface, and outputs upstream analog signals in the 5MHz to 85MHz range to an external PGA.

With its high integration and low-power consumption, the MxL265D enables high-speed broadband data solutions with a compact board design and low BOM cost. The MxL265D IC is controlled through an I2C interface and operates using 3.3V, 1.8V, and 1.1V supplies. The MxL265D is available in a small 7mm x 7mm footprint 48-pin QFN package.

特性 Features

·Full-Spectrum Capture™ (FSC™) cable tuner capable of receiving QAM channels from 44MHz to 1006MHz without external SAW filters
·Remote network monitoring, including spectrum reporting
·SATA-based SerDes interface
·Supports up to 16 downstream channels and 8 upstream channels
·Outputs a DOCSIS upstream signal from 5MHz to 85MHz
·1.6W power consumption in a 16-channel receiver application
·400mW power consumption in a single-channel, LPM with an IF output center frequency that is available from 5MHz to 40MHz
·Downstream channel bandwidth that is configurable to 6MHz or 8MHz
·Reference clock output is provided to the DOCSIS back-end IC for SerDes communication
·I2C-compatible digital control interface
Supported Standards

应用 Application

·EMTAs
·Cable modems
·Cable gateways