MK2732-06GLF集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

Features

• Packaged in 16-pin TSSOP

• Pb (lead) free package

• For xDSL chipsets

• For MPEG2 decoders

• Replaces VCXO and multiplier

• Uses an inexpensive pullable crystal

• On-chip patented VCXO with pull range of 200 ppm

(±100 ppm) minimum

• VCXO tuning voltage of 0 to 3 V

• Zero ppm synthesis error in all clocks

• Full CMOS output swings with 25 mA output drive

capability at TTL levels

• Advanced, low-power, sub-micron CMOS process

• 5 V operating voltage for core, ability to run output clocks

at 3.3 V or 5 V for easy interface.

• Available in commercial and industrial temperature

versions