丝印：MK2049-34SI；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL

Features • Packaged in 20-pin SOIC • 3.3 V + 5 operation • Fixed I/O phase relationship on all selections • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8

文件：256.38 Kbytes 页数：10 Pages

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瑞萨

丝印：MK2049-34SI；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL

Features • Packaged in 20-pin SOIC • 3.3 V + 5 operation • Fixed I/O phase relationship on all selections • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8

文件：256.38 Kbytes 页数：10 Pages

RENESAS

瑞萨

丝印：MK2049-36SILF；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • Pb (lead) free package • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock or

文件：248.79 Kbytes 页数：9 Pages

RENESAS

瑞萨

丝印：MK2049-36SILF；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • Pb (lead) free package • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock or

文件：248.79 Kbytes 页数：9 Pages

RENESAS

瑞萨

丝印：MK2049-45SI；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to

文件：410.92 Kbytes 页数：11 Pages

RENESAS

瑞萨

丝印：MK2049-45SILF；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to

文件：410.92 Kbytes 页数：11 Pages

RENESAS

瑞萨

丝印：MK2049-45SILF；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to

文件：410.92 Kbytes 页数：11 Pages

RENESAS

瑞萨

丝印：MK2049-45SI；Package：SOIC；3.3 VOLT COMMUNICATIONS CLOCK PLL

Features • Packaged in 20 pin SOIC • 3.3 V + 5 operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to

文件：410.92 Kbytes 页数：11 Pages

RENESAS

瑞萨

Communications Clock PLL

Description The MK2049 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference and generates T1, E1, T3, E3, and OC3 frequencies. The device can also accept a T1, E1, T3, or E3 input clock and provide the same output for loop timing. All outputs are

文件：137.06 Kbytes 页数：11 Pages

ICST

Communications Clock PLL

Description The MK2049 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference and generates T1, E1, T3, E3, and OC3 frequencies. The device can also accept a T1, E1, T3, or E3 input clock and provide the same output for loop timing. All outputs are

文件：137.06 Kbytes 页数：11 Pages

ICST