Device User Guide V01.20

Overview The MC9S12DJ64 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 64K bytes of Flash EEPROM, 4K bytes of RAM, 1K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), one seria

文件：1.79605 Mbytes 页数：128 Pages

freescaleFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

MC9S12DJ64 Device User Guide V01.17

Overview The MC9S12DJ64 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 64K bytes of Flash EEPROM, 4K bytes of RAM, 1K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), one seria

文件：1.80912 Mbytes 页数：126 Pages

Motorola

摩托罗拉

MC9S12DJ64 Device User Guide

文件：1.79705 Mbytes 页数：128 Pages

freescaleFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

MC9S12DJ64 Device User GUide V01.17

文件：1.73181 Mbytes 页数：126 Pages

freescaleFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

S12A 16-bit MCU, HCS12 core, 64KB Flash, QFP 80

The MC9S12A512 MCU is a 16-bit device composed of standard on-chip peripherals, including a HCS12 CPU.\nSystem resource mapping, clock generation, interrupt control and bus interfacing are managed by the system integration module (SIM).\nThe MC9S12A512 has full 16-bit data paths throughout, however • 16-bit HCS12 CPU\n• Upward compatible with M68HC11 instruction set\n• Interrupt stacking and programmer's model identical to M68HC11\n• Instruction pipe\n• Enhanced indexed addressing\n• Multiplexed external bus\n• Memory\n• 512 KB flash EEPROM\n• 4 KB EEPROM\n• 14 KB RAM\n• Two asynchronous seria;

恩XP

恩智浦

S12A 16-bit MCU, HCS12 core, 64KB Flash, QFP 112

The MC9S12A512 MCU is a 16-bit device composed of standard on-chip peripherals, including a HCS12 CPU.\nSystem resource mapping, clock generation, interrupt control and bus interfacing are managed by the system integration module (SIM).\nThe MC9S12A512 has full 16-bit data paths throughout, however • 16-bit HCS12 CPU\n• Upward compatible with M68HC11 instruction set\n• Interrupt stacking and programmer's model identical to M68HC11\n• Instruction pipe\n• Enhanced indexed addressing\n• Multiplexed external bus\n• Memory\n• 512 KB flash EEPROM\n• 4 KB EEPROM\n• 14 KB RAM\n• Two asynchronous seria;

恩XP

恩智浦