MC74HCT125A

Quad 3-State Noninverting Buffer with LSTTL Compatible Inputs

TheMC74HCT125AisidenticalinpinouttotheLS125.ThedeviceinputsarecompatiblewithstandardCMOSandLSTTLoutputs. TheMC74HCT125Anoninvertingbufferisdesignedtobeusedwith3−statememoryaddressdrivers,clockdrivers,andotherbus−orientedsystems.Thedeviceshavefourseparate

MC74HCT125A

四路非反相缓冲器，带 LSTTL 兼容输入，3 态; • Output Drive Capability: 15 LSTTL Loads\n• Outputs Directly Interface to CMOS, NMOS, and TTL\n• Operating Voltage Range: 2.0 to 6.0 V\n• Low Input Current: 1.0 µA\n• High Noise Immunity Characteristic of CMOS Devices\n• In Compliance with the JEDEC Standard No. 7A Requirements\n• Chip Complexity: 72 FETs or 18 Equivalent Gates\n• These are PbFree Devices\n;

The MC74HCT125A is identical in pinout to the LS125. The device inputs are compatible with standard CMOS and LSTTL outputs. The MC74HCT125A noninverting buffer is designed to be used with 3 state memory address drivers, clock drivers, and other bus oriented systems. The devices have four separate output enables that are active low.

MC74HCT125A

Quad 3-State Noninverting Buffer

MC74HCT125ADG

Quad 3-State Noninverting Buffer with LSTTL Compatible Inputs

TheMC74HCT125AisidenticalinpinouttotheLS125.ThedeviceinputsarecompatiblewithstandardCMOSandLSTTLoutputs. TheMC74HCT125Anoninvertingbufferisdesignedtobeusedwith3−statememoryaddressdrivers,clockdrivers,andotherbus−orientedsystems.Thedeviceshavefourseparate

MC74HCT125ADR2G

Quad 3-State Noninverting Buffer with LSTTL Compatible Inputs

TheMC74HCT125AisidenticalinpinouttotheLS125.ThedeviceinputsarecompatiblewithstandardCMOSandLSTTLoutputs. TheMC74HCT125Anoninvertingbufferisdesignedtobeusedwith3−statememoryaddressdrivers,clockdrivers,andotherbus−orientedsystems.Thedeviceshavefourseparate

MC74HCT125ADTG

Quad 3-State Noninverting Buffer with LSTTL Compatible Inputs

TheMC74HCT125AisidenticalinpinouttotheLS125.ThedeviceinputsarecompatiblewithstandardCMOSandLSTTLoutputs. TheMC74HCT125Anoninvertingbufferisdesignedtobeusedwith3−statememoryaddressdrivers,clockdrivers,andotherbus−orientedsystems.Thedeviceshavefourseparate

MC74HCT125ADTR2G

Quad 3-State Noninverting Buffer with LSTTL Compatible Inputs

TheMC74HCT125AisidenticalinpinouttotheLS125.ThedeviceinputsarecompatiblewithstandardCMOSandLSTTLoutputs. TheMC74HCT125Anoninvertingbufferisdesignedtobeusedwith3−statememoryaddressdrivers,clockdrivers,andotherbus−orientedsystems.Thedeviceshavefourseparate

MC74HCT125AFELG

Quad 3-State Noninverting Buffer with LSTTL Compatible Inputs

TheMC74HCT125AisidenticalinpinouttotheLS125.ThedeviceinputsarecompatiblewithstandardCMOSandLSTTLoutputs. TheMC74HCT125Anoninvertingbufferisdesignedtobeusedwith3−statememoryaddressdrivers,clockdrivers,andotherbus−orientedsystems.Thedeviceshavefourseparate

MC74HCT125AFG

Quad 3-State Noninverting Buffer with LSTTL Compatible Inputs

TheMC74HCT125AisidenticalinpinouttotheLS125.ThedeviceinputsarecompatiblewithstandardCMOSandLSTTLoutputs. TheMC74HCT125Anoninvertingbufferisdesignedtobeusedwith3−statememoryaddressdrivers,clockdrivers,andotherbus−orientedsystems.Thedeviceshavefourseparate

MC74HCT125ANG

Quad 3-State Noninverting Buffer with LSTTL Compatible Inputs

TheMC74HCT125AisidenticalinpinouttotheLS125.ThedeviceinputsarecompatiblewithstandardCMOSandLSTTLoutputs. TheMC74HCT125Anoninvertingbufferisdesignedtobeusedwith3−statememoryaddressdrivers,clockdrivers,andotherbus−orientedsystems.Thedeviceshavefourseparate