MC68HC705P6ACDW中文资料飞思卡尔数据手册PDF规格书

General Description

Introduction

The MC68HC705P6A is an EPROM version of the MC68HC05P6 microcontroller. It is a low-cost combination of an M68HC05 Family microprocessor with a 4-channel, 8-bit analog-to-digital (A/D) converter, a 16-bit timer with output compare and input capture, a serial communications port (SIOP), and a computer operating properly (COP) watchdog timer. The M68HC05 CPU core contains 176 bytes of RAM, 4672 bytes of user EPROM, 239 bytes of bootloader ROM, and 21 input/output (I/O) pins (20 bidirectional, 1 input-only). This device is available in either a 28-pin plastic dual in-line (PDIP) or a 28-pin small outline integrated circuit (SOIC) package.

A functional block diagram of the MC68HC705P6A is shown in Figure 1-1.

特性 Features

Features of the MC68HC705P6A include:

• Low cost

• M68HC05 core

• 28-pin SOIC, PDIP, or windowed DIP package

• 4672 bytes of user EPROM (including 48 bytes of page zero EPROM and 16 bytes of user vectors)

• 239 bytes of bootloader ROM

• 176 bytes of on-chip RAM

• 4-channel 8-bit A/D converter

• SIOP serial communications port

• 16-bit timer with output compare and input capture

• 20 bidirectional I/O lines and 1 input-only line

• PC0 and PC1 high-current outputs

• Single-chip, bootloader, and test modes

• Power-saving stop, halt, and wait modes

• Static EPROM mask option register (MOR) selectable options:

– COP watchdog timer enable or disable

– Edge-sensitive or edge- and level-sensitive external interrupt

– SIOP most significant bit (MSB) or least significant bit (LSB) first

– SIOP clock rates: OSC divided by 8, 16, 32, or 64

– Stop instruction mode, STOP or HALT

– EPROM security external lockout

– Programmable keyscan (pullups/interrupts) on PA0–PA7