MC68HC11G5CFN中文资料摩托罗拉数据手册PDF规格书

GENERAL DESCRIPTION

The MC68HC11G5, which includes 16 kilobytes of on-board ROM, is a member of the M68HC11 family of advanced capability MCUs. This device has 512 bytes of on-board static RAM and a non multiplexed expanded bus for accessing external memory.

The original MC68HC11 timer system is expanded to contain 3 input capture ports, 4 output compare ports and 3 software selectable input capture or output compare ports. A new 4-channel pulse width modulation timer has been added and there is also an event counter timer system.

1.2 FEATURES OF THE MOTOROLA MC68HC11G5 MCU

• Low-power/high-performance M68HC11 CPU core

• 16 kilobytes of ROM

• 256 bytes of bootstrap ROM

• 512 bytes of static RAM

• RAM, registers and I/O mappable to any 4k boundary

• Expanded non-multiplexed data/address buses give access to a total address space of 64 kilobytes

• Maximum of seven 8-bit, one 6-bit and one 4-bit I/O ports

• 2 separate 16-bit timers, each with its own E-clock divider circuitry

• External clock option on Timer 2

• 4 output compare (OC), 3 input capture (IC) and 3 selectable OC/IC channels

• 4 PWM timers, each with its own counter and programmable period and duty cycle

• Dual event counter featuring phase-shifter, pulse accumulator, periodic timer and 256 clock divider

• 8-channel, 10-bit A/D converter with 1, 4 and 8-channel scanning modes

• COP watchdog timer and clock monitor

• Serial I/O system incorporating asynchronous NRZ and synchronous SPI

• Single Chip, Expanded, Bootstrap and Test modes of operation

• 84-pin PLCC package (quad surface mount plastic)