3-BIT REGISTERED BUS TRANSCEIVER

The MC10E/MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs (BUS0–BUS2) are specified for driving a 25 Ω bus; the receive outputs (Q0 – Q2) are specified for 50 Ω. The bus outputs feature a normal HIGH level (VOH) and a cutoff LOW level — when LOW,

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ONSEMI

安森美半导体

3-BIT REGISTERED BUS TRANSCEIVER

DESCRIPTION The SY10/100E336 offer three bus transceivers with both transmit and receive registers and are designed for use in new, high-performance ECL systems. The bus outputs (BUS0 - BUS2) are designed to drive a 25Ω bus. The receive outputs (Q0 – Q2) are specified for 50Ω. The bus outputs fea

文件：64.28 Kbytes 页数：4 Pages

Micrel

麦瑞半导体

3-BIT REGISTERED BUS TRANSCEIVER

文件：66.04 Kbytes 页数：4 Pages

Micrel

麦瑞半导体

3-BIT REGISTERED BUS TRANSCEIVER

DESCRIPTION The SY10/100E336 offer three bus transceivers with both transmit and receive registers and are designed for use in new, high-performance ECL systems. The bus outputs (BUS0 - BUS2) are designed to drive a 25Ω bus. The receive outputs (Q0 – Q2) are specified for 50Ω. The bus outputs fea

文件：64.28 Kbytes 页数：4 Pages

Micrel

麦瑞半导体