MC100LVEL91

Clock Management Design Using Low Skew and Low Jitter Devices

WhyDoWeNeedClockManagement? CanyouimaginethechaosinourworldifourclocksorwatcheswerenotsynchronizedtoGreenwichMeanTime?Howwouldtrains,buses,andairplanesrunonschedule?TheminiseriesLongitudewasthestoryofamanwhomadeamajortechnologicalbreakthroughbyinv

MC100LVEL91

Triple PECL to ECL Translator?

Description TheMC100LVEL91isatripleLVPECLinputtoECLoutputtranslator.ThedevicereceiveslowvoltagedifferentialPECLsignals,determinedbytheVCCsupplylevel,andtranslatesthemtodifferential−3.3Vto−5.0VECLoutputsignals. ToaccomplishtheleveltranslationtheLVEL91re

MC100LVEL91

3.3 V Triple LVPECL Input to ??.3 V to ??.0 V ECL Output Translator

MC100LVEL91

3.3 V Triple LVPECL Input to -3.3 V to -5.0 V ECL Output Translator

MC100LVEL91_06

3.3 V Triple LVPECL Input to ??.3 V to ??.0 V ECL Output Translator

MC100LVEL91_16

3.3 V Triple LVPECL Input to -3.3 V to -5.0 V ECL Output Translator

MC100LVEL91DW

3.3 V Triple LVPECL Input to ??.3 V to ??.0 V ECL Output Translator

MC100LVEL91DWG

3.3 V Triple LVPECL Input to ??.3 V to ??.0 V ECL Output Translator

MC100LVEL91DWG

3.3 V Triple LVPECL Input to -3.3 V to -5.0 V ECL Output Translator

MC100LVEL91DWR2

3.3 V Triple LVPECL Input to ??.3 V to ??.0 V ECL Output Translator

MC100LVEL91DWR2G

3.3 V Triple LVPECL Input to ??.3 V to ??.0 V ECL Output Translator

MC100LVEL91DWR2G

3.3 V Triple LVPECL Input to -3.3 V to -5.0 V ECL Output Translator

MC100LVEL91DWG

包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 封装/外壳：20-SOIC（0.295"，7.50mm 宽） 类别：集成电路（IC） 转换器，电平移位器 描述：IC TRNSLTR UNIDIRECTIONAL 20SOIC

MC100LVEL91DWR2G

包装：管件 封装/外壳：20-SOIC（0.295"，7.50mm 宽） 类别：集成电路（IC） 转换器，电平移位器 描述：IC TRNSLTR UNIDIRECTIONAL 20SOIC