Dual LVTTL/LVCMOS to Differential LVPECL Translator

Description The MC100EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The small outline 8−lead package and the single gate of the EPT22 makes it ideal for those applications where space, performanc

文件：65.76 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

文件：209.34 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

3.3V Dual LVTTL/LVCMOS to Differential LVPECL to Differential LVPECL

文件：135.95 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

转换器，双 LVTTL / LVCMOS 转换为差分 LVPECL

The MC100EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the single gate of the EPT22 makes it ideal for those applications where space, performance, and low po • 420 ps Typical Propagation Delay\n• Maximum Frequency > 1.1 GHz\n• Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V\n• PNP LVTTL Inputs for Minimal Loading\n• Q Output will default HIGH with inputs open\n• The 100 Series contains temperature compensation.\n• Pb-Free Packages are Available;

ONSEMI

安森美半导体

Dual LVTTL/LVCMOS to Differential LVPECL Translator

Description The MC100EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The small outline 8−lead package and the single gate of the EPT22 makes it ideal for those applications where space, performanc

文件：65.76 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

Dual LVTTL/LVCMOS to Differential LVPECL Translator

Description The MC100EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The small outline 8−lead package and the single gate of the EPT22 makes it ideal for those applications where space, performanc

文件：65.76 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

3.3V Dual LVTTL/LVCMOS to Differential LVPECL to Differential LVPECL

文件：135.95 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator

文件：362.5 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Evaluation Board Manual for High Frequency SOIC 8

文件：202.47 Kbytes 页数：20 Pages

ONSEMI

安森美半导体

3.3V Dual LVTTL/LVCMOS to Differential LVPECL to Differential LVPECL

文件：135.95 Kbytes 页数：8 Pages

ONSEMI

安森美半导体