MC100EP14

时钟驱动器，1:5 差分，ECL / HSTL，3.3 V / 5.0 V; • 400 ps Typical Propagation Delay\n• 100 ps Device-to-Device Skew\n• 25 ps Within Device Skew\n• Maximum Frequency > 2 GHz Typical\n• The 100 Series Contains Temperature Compensation\n• PECL and HSTL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V\n• NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V\n• Open Input Default State\n;

The MC100EP14 is a low skew 1-to-5differential driver, designed with clock distribution in mind, accepting two clock sources into an inputmultiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions.The EP14 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device.To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.The common enable (ENbar) is synchronous, outputs are enabled/disabled in the LOW state. This avoids a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is locked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

MC100EP14

3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver

MC100EP14

3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver

MC100EP140

相位频率检测器，3.3 V，ECL; • 500 ps Typical Propagation Delay\n• Maximum Frequency > 2.1 Ghz Typical\n• Fully Differential Internally\n• Advanced High Band Output Swing of 400 mV\n• Transfer Gain: 1.0 mV/Degree at 1.4 GHz, 1.2 mV/Degree at 1.0 GHz\n• Rise and Fall Time: 100 ps Typical\n• The 100 Series Contains Temperature Compensation\n• PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V\n• Open Input Default State\n• Pb-Free Packages are Available\n;

The MC100EP140 is a three state phase frequency-detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. Since the part is designed with fully differential gates, the noise is reduced throughout the circuit, especially at high speeds. The basic operation of a Phase/Frequency Detector (PFD) is to \"compare\" an incoming signal (feedback) to a set reference signal. When the Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase, the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO.The device is packaged in a small outline, surface mount 8-lead SOIC package. The output of the EP140 is 400 mV, which allows faster switching time and greater bandwidth. This device can also be used in +3.3 V systems. For proper operation, the input edge rate of the R and FB inputs should be less than 5 ns.More information on Phase Lock Loop operation and application can be found in AND8040.

MC100EP142

ECL 9 位移位寄存器; • > 3 GHz Minimum Shift Frequency\n• 9-Bit for Byte-Parity Applications\n• Asynchronous Master Reset\n• Dual Clocks\n• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = –3.0 V to –5.5 V\n• Open Input Default State\n• Safety Clamp on Inputs\n;

The MC10EP/100EP142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in andserial/parallel out, shifting in one direction. The nine inputs D0 - D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.The SEL (Select) input pin is used to switch between the two modes of operation - SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK0 or CLK1; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the resisters to zero.The 100 Series contains temperature compensation.

MC100EP142FA

3.3 V / 5 V ECL 9-Bit Shift Register

3.3V/5VECL9−BitShiftRegister TheMC10EP/100EP142isa9−bitshiftregister,designedwithbyte-parityapplicationsinmind.TheMC10/100EP142iscapableofperformingserial/paralleldataintoserial/paralleloutandshiftinginonlyonedirection.ThenineinputsD0−D8acceptparallel

MC100EP142FAG

3.3 V / 5 V ECL 9-Bit Shift Register

3.3V/5VECL9−BitShiftRegister TheMC10EP/100EP142isa9−bitshiftregister,designedwithbyte-parityapplicationsinmind.TheMC10/100EP142iscapableofperformingserial/paralleldataintoserial/paralleloutandshiftinginonlyonedirection.ThenineinputsD0−D8acceptparallel

MC100EP142FAR2

3.3 V / 5 V ECL 9-Bit Shift Register

3.3V/5VECL9−BitShiftRegister TheMC10EP/100EP142isa9−bitshiftregister,designedwithbyte-parityapplicationsinmind.TheMC10/100EP142iscapableofperformingserial/paralleldataintoserial/paralleloutandshiftinginonlyonedirection.ThenineinputsD0−D8acceptparallel

MC100EP142FAR2G

3.3 V / 5 V ECL 9-Bit Shift Register

3.3V/5VECL9−BitShiftRegister TheMC10EP/100EP142isa9−bitshiftregister,designedwithbyte-parityapplicationsinmind.TheMC10/100EP142iscapableofperformingserial/paralleldataintoserial/paralleloutandshiftinginonlyonedirection.ThenineinputsD0−D8acceptparallel

MC100EP142MNG

3.3 V / 5 V ECL 9-Bit Shift Register

3.3V/5VECL9−BitShiftRegister TheMC10EP/100EP142isa9−bitshiftregister,designedwithbyte-parityapplicationsinmind.TheMC10/100EP142iscapableofperformingserial/paralleldataintoserial/paralleloutandshiftinginonlyonedirection.ThenineinputsD0−D8acceptparallel