3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver

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3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver

文件：132.37 Kbytes 页数：9 Pages

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时钟驱动器，1:5 差分，ECL / HSTL，3.3 V / 5.0 V

The MC100EP14 is a low skew 1-to-5differential driver, designed with clock distribution in mind, accepting two clock sources into an inputmultiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operati • 400 ps Typical Propagation Delay\n• 100 ps Device-to-Device Skew\n• 25 ps Within Device Skew\n• Maximum Frequency > 2 GHz Typical\n• The 100 Series Contains Temperature Compensation\n• PECL and HSTL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V\n• NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V\n• Op;

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3.3 V / 5 V ECL 9-Bit Shift Register

3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel

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3.3 V / 5 V ECL 9-Bit Shift Register

3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel

文件：176.4 Kbytes 页数：13 Pages

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3.3 V / 5 V ECL 9-Bit Shift Register

3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel

文件：176.4 Kbytes 页数：13 Pages

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安森美半导体

3.3 V / 5 V ECL 9-Bit Shift Register

3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel

文件：176.4 Kbytes 页数：13 Pages

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安森美半导体

3.3 V / 5 V ECL 9-Bit Shift Register

3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel

文件：176.4 Kbytes 页数：13 Pages

ONSEMI

安森美半导体

3.3 V / 5 V ECL 9-Bit Shift Register

3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel

文件：176.4 Kbytes 页数：13 Pages

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安森美半导体

3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver

文件：132.37 Kbytes 页数：9 Pages

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安森美半导体