MC100EP1

3.3V / 5V ECL Quad 2-Input Differential AND/NAND

Description TheMC10/100EP105isaquad2−inputdifferentialAND/NANDgate.EachgateisfunctionallyequivalenttotheEP05andLVEL05devices.WithACperformancemuchfasterthantheLVEL05device,theEP105isidealforapplicationsrequiringthefastestACperformanceavailable. The100Ser

MC100EP105

3.3V / 5V ECL Quad 2-Input Differential AND/NAND

Description TheMC10/100EP105isaquad2−inputdifferentialAND/NANDgate.EachgateisfunctionallyequivalenttotheEP05andLVEL05devices.WithACperformancemuchfasterthantheLVEL05device,theEP105isidealforapplicationsrequiringthefastestACperformanceavailable. The100Ser

MC100EP105

ECL Quad 2-Input Differential AND/NAND Gate; • 275ps Typical Propagation Delay\n• Maximum Frequency > 3 Ghz Typical\n• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V\n• Open Input Default State\n• Safety Clamp on Inputs\n• Pb-Free Packages are Available\n;

The MC10/100EP105 is a quad 2-input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available.The 100 Series contains temperature compensation.

MC100EP105FA

3.3V / 5V ECL Quad 2-Input Differential AND/NAND

Description TheMC10/100EP105isaquad2−inputdifferentialAND/NANDgate.EachgateisfunctionallyequivalenttotheEP05andLVEL05devices.WithACperformancemuchfasterthantheLVEL05device,theEP105isidealforapplicationsrequiringthefastestACperformanceavailable. The100Ser

MC100EP105FAR2

3.3V / 5V ECL Quad 2-Input Differential AND/NAND

Description TheMC10/100EP105isaquad2−inputdifferentialAND/NANDgate.EachgateisfunctionallyequivalenttotheEP05andLVEL05devices.WithACperformancemuchfasterthantheLVEL05device,theEP105isidealforapplicationsrequiringthefastestACperformanceavailable. The100Ser

MC100EP11

Clock / Data Fanout Buffer, 1:2 Differential, ECL, 3.3 V / 5.0 V; • 220 ps Typical Propagation Delay\n• Maximum Frequency > 3 GHz Typical\n• PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V\n• NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V\n• Open Input Default State\n• Safety Clamp on Inputs\n• Q Outputs Will Default LOW with Inputs Open or at VEE\n;

The MC10EP11 is a differential 1 to 2 fanout buffer. The device is pin and functionally equivalent to the LVEL11 device. With AC performance much faster than the LVEL11 device, the EP11 is ideal for applications requiring the fastest AC performance available.

MC100EP116

Differential Line Receiver / Driver; • 260 ps Typical Propagation Delay\n• Maximum Frequency > 3 GHz Typical\n• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE =-3.0 V to -5.5 V\n• Open Input Default State\n• Safety Clamp on Inputs\n• Q Output will default LOW with inputs open or at VEE\n• VBB Output\n;

The MC10EP116/100EP116 is a 6-bit differential line receiver based on the EP16 device. The 3.0GHz bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.The differential inputs have internal clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state. Thus, inputs of unused gates can be left open and will not affect the operation of the rest of the device. Note that the input clamp will take affect only if both inputs fall 2.5V below VCC.The 100 Series contains temperature compensation.

MC100EP131

3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock

Description TheMC10/100EP131isaQuadMaster−slavedDflip−flopwithcommonsetandseparateresets.ThedeviceisanexpansionoftheE131withdifferentialcommonclockandindividualclockenables.WithACperformancefasterthantheE131device,theEP131isidealforapplicationsrequiring

MC100EP131FA

3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock

Description TheMC10/100EP131isaQuadMaster−slavedDflip−flopwithcommonsetandseparateresets.ThedeviceisanexpansionoftheE131withdifferentialcommonclockandindividualclockenables.WithACperformancefasterthantheE131device,theEP131isidealforapplicationsrequiring

MC100EP131FAR2

3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock

Description TheMC10/100EP131isaQuadMaster−slavedDflip−flopwithcommonsetandseparateresets.ThedeviceisanexpansionoftheE131withdifferentialcommonclockandindividualclockenables.WithACperformancefasterthantheE131device,theEP131isidealforapplicationsrequiring