MB90V550A中文资料富士通数据手册PDF规格书

■ DESCRIPTION

The MB90550A/550B series is a line of general-purpose, high-performance, 16-bit microcontrollers designed for applications which require high-speed real-time processing, such as industrial machines, OA equipment, and process control systems.

While inheriting the AT architecture of the F2MC*-8 family, the instruction set for the MB90550A/550B series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90550A/550B has an on-chip 32-bit accumulator which enables processing of long-word data.

MB90552B and MB90553B are radiation noise decreased type. There are no change in the functional specification.

■ FEATURES

• Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, × four times the PLL clock)

• Maximum memory space: 16 Mbytes

• Instruction set optimized for controller applications

Supported data types: Bit, byte, word and long word

Typical addressing mode: 23 types

Enhanced precision calculation realized by 32-bit accumulator

Enhanced signed multiplication/division instruction and RETI instruction functions

• Instruction set designed for high level language (C) and multi-task operations

Adoption of system stack pointer

Symmetrical instruction set and barrel shift instructions

• Integrated address match detection function (for two address pointers)

• Faster execution speed: 4-byte queue

• Powerful interrupt functions (Eight priority levels programmable)

External interrupt inputs: 8 channels

• Data transfer functions (Intelligent I/O service): Up to 16 channels DTP request inputs: 8 channels

• Embedded ROM size (EPROM, Flash: 128 Kbytes)

Mask ROM: 64 Kbytes/128 Kbytes

• Embedded RAM size (EPROM, Flash: 4 Kbytes)

Mask ROM: 2 Kbytes/4 Kbytes

• General-purpose ports: Up to 83 channels

(Input pull-up resistor settable for: 16 channels; Open drain settable for: 8 channels; I/O open drains: 6 channels)

• A/D converter (RC successive approximation type): 8 channels

(Resolution: 8 or 10 bits selectable; Conversion time of 26.3 µs minimum)

• UART: 1 channel

• Extended I/O serial interface: 2 channels

• I2C interface: 2 channels

(Two channels, including one switchable between terminal input and output)

• 16-bit reload timer: 2 channels

• 8/16-bit PPG timer: 3 channels

(8 bits × 2 channels; 16 bits x 1 channel: Mode switching function provided)

• 16-bit I/O timer (Input capture × 4 channels, output compare × 4 channels, free run timer ×1 channel)

• Clock monitor function integrated (Delivering the oscillation clock divided by 21 to 28)

• Timebase timer/watchdog timer: 18 bits

• Low power consumption modes (sleep, stop, hardware standby, and CPU intermittent operation modes)

• Package: QFP-100, LQFP-100

• CMOS technology