HEX SCHMITT INVERTER

DESCRIPTION The M54/74HC14 is a high speed CMOS HEX SCHMITT INVERTER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. Pin configuration and function are the same as those of the HC04 but all inputs have 20

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HEX SCHMITT INVERTER

DESCRIPTION The M74HC14 is an high speed CMOS HEX SCHMITT INVERTER fabricated with silicon gate C2MOS technology. Pin configuration and function are the same as those of the M74HC04 but all inputs have 20 Vcc hysteresis level. This, together with its schmitt trigger function, allows it to be us

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Hex Schmitt inverter

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Hex Schmitt Inverter

The M74HC14 is a high speed CMOS hex Schmitt inverter fabricated with silicon gate C2MOS technology. Pin configuration and functions are the same as those of the M74HC04 but all inputs have a 20 % VCC hysteresis level.\nThis, together with the Schmitt trigger function, allows the device to be us High speed: t\nPD = 12 ns (typ.) at V\nCC = 6 V \nLow power dissipation: I\nCC = 1 μA (max.) at T\nA = 25 °C \nHigh noise immunity: V\nH = 1.2 V (typ.) at V\nCC = 6 V \nSymmetrical output impedance: |I\nOH| = I\nOL = 4 mA (min.) \nBalanced propagation delays: t\nPLH ≃ t\nPHL\nWide operating voltage ;

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10 TO 4 LINE PRIORITY ENCODER

DESCRIPTION The M54/74HC147 is a high speed CMOS 10 TO 4 LINE PRIORITY ENCODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device features priority encoding of the inputs to ensure that only the

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10 TO 4 LINE PRIORITY ENCODER

DESCRIPTION The M54/74HC147 is a high speed CMOS 10 TO 4 LINE PRIORITY ENCODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device features priority encoding of the inputs to ensure that only the

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10 TO 4 LINE PRIORITY ENCODER

DESCRIPTION The M54/74HC147 is a high speed CMOS 10 TO 4 LINE PRIORITY ENCODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device features priority encoding of the inputs to ensure that only the

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10 TO 4 LINE PRIORITY ENCODER

DESCRIPTION The M54/74HC147 is a high speed CMOS 10 TO 4 LINE PRIORITY ENCODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This device features priority encoding of the inputs to ensure that only the

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8 TO 3 LINE PRIORITY ENCODER

The M54/74HC148 is a high speed CMOS 8-TO-3 LINE PRIORITY ENCODER fabricated in silicon gate C2 MOS technology. It has the same high speed performance for LSTTL combined with true CMOS low power consumption. The M54/74HC148 encodes eight data lines to three-line (4-2-1) binary (octal). Casca

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8 TO 3 LINE PRIORITY ENCODER

The M54/74HC148 is a high speed CMOS 8-TO-3 LINE PRIORITY ENCODER fabricated in silicon gate C2 MOS technology. It has the same high speed performance for LSTTL combined with true CMOS low power consumption. The M54/74HC148 encodes eight data lines to three-line (4-2-1) binary (octal). Casca

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