M36W0R5020T0ZAQT中文资料意法半导体数据手册PDF规格书

SUMMARY DESCRIPTION

The M36W0R5020T0 and M36W0R5020B0 combine two memory devices in a Multi-Chip Package:

■ a 32-Mbit, Multiple Bank Flash memory, the M58WR032FT/B

■ and a 4-Mbit SRAM.

Recommended operating conditions do not allow more than one memory to be active at the same time.

FEATURES SUMMARY

■ MULTI-CHIP PACKAGE

– 1 die of 32 Mbit (2Mb x 16) Flash Memory

– 1 die of 4 Mbit (256Kb x16) SRAM

■ SUPPLY VOLTAGE

– VDDF = VDDQ = VDDS = 1.7 to 1.95V

■ LOW POWER CONSUMPTION

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code (Top Flash Configuration): 8814h

– Device Code (Bottom Flash Configuration): 8815h

■ PACKAGE

– Compliant with Lead-Free Soldering Processes

– Lead-Free Versions

FLASH MEMORY

■ PROGRAMMING TIME

– 8µs by Word typical for Fast Factory Program

– Double/Quadruple Word Program option

– Enhanced Factory Program options

■ MEMORY BLOCKS

– Multiple Bank Memory Array: 4 Mbit Banks

– Parameter Blocks (Top or Bottom location)

■ SYNCHRONOUS / ASYNCHRONOUS READ

– Synchronous Burst Read mode: 66MHz

– Asynchronous/ Synchronous Page Read mode

– Random Access: 70ns

■ DUAL OPERATIONS

– Program Erase in one Bank while Read in others

– No delay between Read and Write operations

■ BLOCK LOCKING

– All blocks locked at Power-up

– Any combination of blocks can be locked

– WPF for Block Lock-Down

■ SECURITY

– 128-bit user programmable OTP cells

– 64-bit unique device number

■ COMMON FLASH INTERFACE (CFI)

■ 100,000 PROGRAM/ERASE CYCLES per BLOCK

SRAM

■ ACCESS TIME: 70ns

■ LOW VDDS DATA RETENTION: 1.0V

■ POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS