M24C64-FDW6集成电路（IC）的存储器规格书PDF中文资料

M24C64-FDW6属于集成电路（IC）的存储器。由意法半导体集团制造生产的M24C64-FDW6存储器存储器是集成电路上用作数据存储设备的半导体器件。这些器件分为非易失性或易失性两种，格式包括 CBRAM、DRAM、EEPROM、EERAM、EPROM、闪存、FRAM、NVSRAM、PCM (PRAM)、PSRAM、RAM 和 SRAM。这些器件的存储容量为 64 b 至 6 Tb 不等，接口有 I2C、MMC、并行、eMMC、串行、单线、SPI、UFS、Xccela 总线和 1-线。

特性 Features

■ Supports the I2C bus 100 kHz Standard-mode and 400 kHz Fast-mode

■ Single supply voltages (see Table 1 for root part numbers):

– 2.5 V to 5.5 V

– 1.8 V to 5.5 V

– 1.7 V to 5.5 V

■ Write Control input

■ Byte and Page Write

■ Random and Sequential Read modes

■ Self-timed programming cycle

■ Automatic address incrementing

■ Enhanced ESD/latch-up protection

■ More than 1 Million write cycles

■ More than 40-year data retention

■ Packages

– ECOPACK® (RoHS compliant)

描述 Description

The M24C32, M24C64 and M24128 devices are I2C-compatible electrically erasable programmable memories (EEPROM). They are organized as 4096 × 8 bits, 8192 × 8 bits and 16384 × 8 bits, respectively.

I2C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition.

The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW) (as described in Table 3), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.