LMK1D2106RHAT集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

LMK1D2106RHAT属于集成电路（IC）的时钟缓冲器驱动器。由德州仪器制造生产的LMK1D2106RHAT时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。

1 Features

• High-performance LVDS clock buffer family: up to

2 GHz

– Dual 1:6 differential buffer

– Dual 1:8 differential buffer

• Supply voltage: 1.71 V to 3.465 V

• Low additive jitter: < 60 fs RMS maximum in 12-

kHz to

20-MHz at 156.25 MHz

– Very low phase noise floor: -164 dBc/Hz

(typical)

• Very low propagation delay: < 575 ps maximum

• Output skew: 20 ps maximum

• High-swing LVDS (boosted mode): 500-mV VOD

typical when AMP_SEL = 1

• Bank enable/disable using the EN pin

• Fail-safe input operation

• Universal inputs accept LVDS, LVPECL, LVCMOS,

HCSL and CML signal levels

• LVDS reference voltage, VAC_REF, available for

capacitive-coupled inputs

• Industrial temperature range: –40°C to 105°C

• Packaged in

– LMK1D2106: 6-mm × 6-mm, 40-pin VQFN

(RHA)

– LMK1D2108: 7-mm × 7-mm, 48-pin VQFN

(RGZ)

2 Applications

• Telecommunications and networking

• Medical imaging

• Test and measurement

• Wireless infrastructure

• Pro audio, video and signage

3 Description

The LMK1D210x clock buffer distributes two clock

inputs (IN0 and IN1) to a total of 16 pairs of

differential LVDS clock outputs (OUT0 to OUT15) in

the LMK1D2108 and 12 pairs of clock outputs (OUT0

to OUT11) in the LMK1D2106 with minimum skew

for clock distribution. Each buffer block consists of

one input and a maximum of 6 (LMK1D2106) or 8

(LMK1D2108) LVDS outputs. The inputs can either be

LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210x is specifically designed for driving

50-Ω transmission lines. When driving inputs in

single-ended mode, apply the appropriate bias

voltage to the unused negative input pin (see Figure

8-6).

Using the control pin (EN), output banks can either be

enable or disabled. If this pin is left open, both bank

outputs are enabled. If the control pin is switched to a

logic 0, both bank outputs are disabled (static logic

0). If the control pin is switched to a logic 1, the

outputs of one bank are disabled while the outputs of

the other bank are enabled. The part also supports a

fail-safe function. The device further incorporates an

input hysteresis which prevents random oscillation of

the outputs in the absence of an input signal.

The device operates in a 1.8-V, 2.5-V, or 3.3-V

supply environment and is characterized from –40°C

to 105°C (ambient temperature).