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LMK1D2106RHAR.B中文资料德州仪器数据手册PDF规格书

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厂商型号

LMK1D2106RHAR.B

功能描述

LMK1D210x Low Additive Jitter LVDS Buffer

丝印标识

LMK1D2106

封装外壳

VQFN(RHA)

文件大小

2.95165 Mbytes

页面数量

37

生产厂商

TI

中文名称

德州仪器

网址

网址

数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-11-2 17:36:00

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LMK1D2106RHAR.B规格书详情

1 Features

• High-performance LVDS clock buffer family: up to

2 GHz

– Dual 1:6 differential buffer

– Dual 1:8 differential buffer

• Supply voltage: 1.71 V to 3.465 V

• Low additive jitter: < 60 fs RMS maximum in 12-

kHz to

20-MHz at 156.25 MHz

– Very low phase noise floor: -164 dBc/Hz

(typical)

• Very low propagation delay: < 575 ps maximum

• Output skew: 20 ps maximum

• High-swing LVDS (boosted mode): 500-mV VOD

typical when AMP_SEL = 1

• Bank enable/disable using the EN pin

• Fail-safe input operation

• Universal inputs accept LVDS, LVPECL, LVCMOS,

HCSL and CML signal levels

• LVDS reference voltage, VAC_REF, available for

capacitive-coupled inputs

• Industrial temperature range: –40°C to 105°C

• Packaged in

– LMK1D2106: 6-mm × 6-mm, 40-pin VQFN

(RHA)

– LMK1D2108: 7-mm × 7-mm, 48-pin VQFN

(RGZ)

2 Applications

• Telecommunications and networking

• Medical imaging

• Test and measurement

• Wireless infrastructure

• Pro audio, video and signage

3 Description

The LMK1D210x clock buffer distributes two clock

inputs (IN0 and IN1) to a total of 16 pairs of

differential LVDS clock outputs (OUT0 to OUT15) in

the LMK1D2108 and 12 pairs of clock outputs (OUT0

to OUT11) in the LMK1D2106 with minimum skew

for clock distribution. Each buffer block consists of

one input and a maximum of 6 (LMK1D2106) or 8

(LMK1D2108) LVDS outputs. The inputs can either be

LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210x is specifically designed for driving

50-Ω transmission lines. When driving inputs in

single-ended mode, apply the appropriate bias

voltage to the unused negative input pin (see Figure

8-6).

Using the control pin (EN), output banks can either be

enable or disabled. If this pin is left open, both bank

outputs are enabled. If the control pin is switched to a

logic 0, both bank outputs are disabled (static logic

0). If the control pin is switched to a logic 1, the

outputs of one bank are disabled while the outputs of

the other bank are enabled. The part also supports a

fail-safe function. The device further incorporates an

input hysteresis which prevents random oscillation of

the outputs in the absence of an input signal.

The device operates in a 1.8-V, 2.5-V, or 3.3-V

supply environment and is characterized from –40°C

to 105°C (ambient temperature).

供应商 型号 品牌 批号 封装 库存 备注 价格
TAIYO/太诱
2025+
SMD
16854648
代理销售TAIYO/太诱原装现货
询价
TAIYO/太诱
22+
SMD
3000
原装正品,支持实单
询价
TI原装
24+
VQFN48
18000
原装正品 有挂有货 假一赔十
询价
TAIYO/太诱
25+
SMD
860000
明嘉莱只做原装正品现货
询价
TAIYO/太诱
22+
SMD
18000
原装正品
询价
TI/德州仪器
25+
原厂封装
10280
原厂授权代理,专注军工、汽车、医疗、工业、新能源!
询价
TI(德州仪器)
24+
VQFN40(6x6)
1652
原装现货,免费供样,技术支持,原厂对接
询价
TAIYO/太诱
2447
0805-106K10V
100500
一级代理专营品牌!原装正品,优势现货,长期排单到货
询价
TAIYO YUDEN
2109
con
11829
现货常备产品原装可到京北通宇商城查价格
询价
TAIYO/太诱
21+
SMD
3000
只做原装正品,不止网上数量,欢迎电话微信查询!
询价