Digitally-Controlled Stereo Tone and Volume Circuit with Two Selectable Stereo Inputs

文件：348.46 Kbytes 页数：14 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

Digitally-Controlled Stereo Tone and Volume Circuit with Two Selectable Stereo Inputs

文件：348.46 Kbytes 页数：14 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

Multi-Rate Video Clock Generator with Genlock

文件：504.41 Kbytes 页数：28 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

LMH1982 Multi-Rate Video Clock Generator With Genlock

1 Features 1• Two Simultaneous LVDS Output Clocks with Selectable Frequencies and Hi-Z Capability: – SD Clock: 27 MHz or 67.5 MHz – HD Clock: 74.25 MHz, 74.25/1.001 MHz, 148.5 MHz or 148.5/1.001 MHz • Low-Jitter Output Clocks May Be Directly Connected to an FPGA Serializer to Meet SMPTE SD

文件：696.79 Kbytes 页数：48 Pages

TI

德州仪器