512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件：1.97506 Mbytes 页数：39 Pages

ISSI

矽成半导体

512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件：1.97506 Mbytes 页数：39 Pages

ISSI

矽成半导体

512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件：1.97506 Mbytes 页数：39 Pages

ISSI

矽成半导体

512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件：1.97506 Mbytes 页数：39 Pages

ISSI

矽成半导体

512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件：1.97506 Mbytes 页数：39 Pages

ISSI

矽成半导体

512 K x36 and 1024 K x18 18 Mb PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件：1.97506 Mbytes 页数：39 Pages

ISSI

矽成半导体

Synchronous SRAM

·4Mb, 9Mb, 18Mb, 36Mb, and 72Mb densities available\n·x18, x36, and x72 configurations available\n·Pipeline, Flow-Through, and No-Wait State (ZBT equivalent)\n·Commercial, Industrial, and Automotive Temperature support\n·ECC feature available for 4Mb product\n·250MHz speed for Pipeline\n·6.5ns acces

ISSI

矽成半导体

Package：165-TBGA；包装：托盘 类别：集成电路（IC） 存储器 描述：IC SRAM 18MBIT PARALLEL 165TFBGA

ISSI, Integrated Silicon Solution Inc

Package：165-TBGA；包装：卷带（TR） 类别：集成电路（IC） 存储器 描述：IC SRAM 18MBIT PARALLEL 165TFBGA

ISSI, Integrated Silicon Solution Inc

Package：165-TBGA；包装：托盘 类别：集成电路（IC） 存储器 描述：IC SRAM 18MBIT PARALLEL 165TFBGA

ISSI, Integrated Silicon Solution Inc